1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit (IC), and more particularly to a method of fabricating an isolation structure to isolate devices in order that the devices can normally operate.
2. Description of the Related Art
A complete IC is composed of thousands of transistors. To prevent short circuit occurring between adjacent transistors, isolation structures have to be formed to isolate the transistors. Isolation structures are usually in the form of thick oxide, which are formed on the surface of the semiconductor substrate. One of the most commonly used isolation structures is local oxidation of silicon (LOCOS). The LOCOS technique is now a mature technique with lower cost and high reliability. However, some drawbacks of the LOCOS technique still exist, including undesired stress and bird's beak. Especially, bird's beak results in noneffective isolation for small size devices. Therefore, it is not suitable for high density semiconductor devices.
Shallow trench isolation (STI) structures are now widely used for IC devices isolation. Typically, silicon nitride is used as a hard mask to etch the semiconductor substrate anisotropically to form a substantially vertical trench. Then, the trench is filled with oxide to be a device isolation structure. The upper surface of the isolation structure is about at the same level as the upper surface of the original substrate. The thickness of the STI structure provides effective isolation and is suitable for smaller size devices. Also, the STI technique provides a overall planarized surface. Therefore, the STI structure takes place of the conventional LOCOS structure to be applied in a number of device isolation techniques such as dynamic random access memory (DRAM).
A conventional process for fabricating a STI structure is illustrated as followed.
Referring to FIG. 1A, a pad oxide layer 11 and a silicon nitride layer 12 are successively formed over the substrate 10. Next, after forming a photoresist layer 13, the substrate 10 is then patterned by anisotropically etching, using the photoresist layer 13 as a mask so that a trench 14 is formed. The trench 14 has a periphery and exposes the inner surface of the substrate 10.
Next, referring to FIG. 1B, after removing the photoresist layer 12, a thermal oxidation process is performed. The substrate 10 is placed at a furnace containing dry oxygen, at a temperature of about 850.about.950.degree. C. so that an oxide layer 16 is formed to cover the trench 14. The oxide layer 16 is a silicon dioxide layer, with a thickness of about 200.about.600 .ANG.. This oxide layer 16 is used as liner oxide. Then, an insulating layer 17 is deposited by low pressure chemical vapor deposition (LPCVD), which covers the oxide layer 16. The insulating layer 17 is an oxide produced by using the TEOS as gas source. The oxide is then processed through densification.
Next, referring to FIG. 1C, the insulating layer 17 and the silicon nitride layer 12 are polished by chemical mechanical polishing (CMP) until substantially a portion of the silicon nitride layer 12 is left on the substrate 10 wherein the remaining silicon nitride layer 12 has a thickness of about hundreds of .ANG.. Then, a conventional cleaning step, using fluoric acid solution to wash the exposed substrate 10, is performed to obtain hydrophobic substrate surface. Alternatively, using perhydroxyl oxide to wash the exposed substrate 10 to obtain a hydrophilic substrate surface.
Next, referring to FIG. 1D, oxygen is introduced into a furnace at a temperature of about 850.about.950.degree. C. to form a sacrificial oxide layer 18, covering the substrate 10, the insulating layer 17a. Conventional ion implantation processes are then performed to form wells and channel stop layer(not shown) at the substrate 10 and also to adjust the threshold voltage. Diluted fluoric acid is then used to wash the substrate and to remove the sacrificial oxide layer 18. A gate oxide layer 18' shown in FIG. 1E is then formed in a furnace.
Generally, during the process of using the flouric acid to wash the sacrificial oxide layer 18, the oxide layer 16 is usually over etched because the difference of the etching rate of the sacrificial oxide layer and the liner oxide layer 16. As a result, the upper surface of the oxide layer 16 around the periphery of the trench becomes lower than the upper surface of the substrate, as shown in FIG. 1E. Overetching occurring at the junction of the oxide layer 16 and the surface of the substrate 10 forms concave 19. In the continuing processes, as a conductive structure is formed over the concave 19, the current in the conductive structure will flow into other device structure, which results in an undesired electrical coupling of the devices and the conductive structure. This effect is so-called kink effect.
The STI structure has been widely for the process of less than 0.25 .mu.m. However, the most serious problem is that concave usually forms at the periphery of the trench as the flouric acid is usually for cleaning the sacrificial oxide layer, which results in so-called subthreshold kink effect. Especially, during the process of dual gate oxide layer, the problem caused by flouric acid washing becomes even more serious. Within the processes of forming n-type and p-type gate, the kink effect of the PMOS is more serious than the kink effect of the NMOS because the doping dosage of phosphorous or arsenic in the n-well is higher than the doping dosage of boron or flouric boron in the p-well, the damage of the oxide for the PMOS STI structure is more serious and the concave becomes more apparent.